(a). Field of the Invention
The present invention relates to a non-volatile semiconductor memory device such as flash EEPROM, more in particular to the non-volatile sem-iconductor memory device having a function of selecting a group of word lines.
(b). Description of the Related Art
A conventional flash EEPROM includes a memory cell array having a plurality of non-volatile memory cells located at the respective intersections in a matrix formed by a plurality of word lines and a plurality of bit lines. The EEPROM has a row decoder connected to each of the memory cells through a corresponding word line extending in the row direction and a program circuit connected to each of the memory cells through source lines and bit lines both extending perpendicular to the word lines.
The memory cell array of the EEPROM may have first and second select transistors, a cell transistor constituting the memory cell and the word lines connected to the respective gates of the first and second select transistors. The first select transistor includes a current path having an end connected to the source line and the other end connected to the control gate of the cell transistor. The second select transistor includes a current path having an end connected to the bit line and the other end connected to one end of the current path of the cell transistor The row decoder selects the word line in accordance with a supplied address signal, and the programming circuit selects the source line and the bit line in accordance with a specified signal.
When the programming mode is selected in the above conventional EEPROM, the gate of the select transistor of the selected memory cell is biased to HIGH through the word line to turn ON the select transistor. Since the programming circuit biases one end of the current path of the first select transistor through the source line, for example, to 0V, the control gate of the select transistor is biased to 0V. Since, simultaneously, the programming circuit biases one end of the current path of the second select transistor through the bit line to HIGH, the drain of the cell transistor is biased to somewhat lower HIGH, and the programming is conducted by extracting electric charges from a floating gate.
When an erasing mode is selected, both of the gates of the first and second select transistors in the selected memory cell are biased to HIGH through the word lines to turn ON the transistors. Since, at this time, the programming circuit biases one end of the current path of the first select transistor to HIGH through the source line, the control gate of the cell transistor is biased to somewhat lower HIGH. Since the programming circuit biases one end of the current path of the second select transistor through the bit line, for example, to 0V, one end of the current path of the cell transistor is biased to 0V through the second select transistor. Thereby, electric charges are injected into the floating gate of the first select transistor to perform a flash erasing.
Due to the fact that the programming and the erasing are conducted by the extraction and the injection of the electric charges from and to the floating gate, the time required for the programming and the erasing in the conventional EEPROM is longer than that required for the reading, and is also longer than those of the reading in the case of DRAM (Dynamic RAM) and SRAM (Static RAM) Specifically, the time length required for the programming and the erasing of one word in DRAM and SRAM is several nanoseconds, whereas the time length in EEPROM is several microseconds. Although the flash erasing can be conducted in about one second, the flash programming is hardly conducted without a specific structure.
When EEPROM is forwarded as a manufactured product, the inspection whether or not memory cells correctly operate at all bits (for example, 1M bits). This inspection requires several tens of seconds, and the cost of the product elevates. Therefore, EEPROM is highly desired having a function of enabling the flash programming and the flash erasing and of reducing the time length required for the inspection without a specific structure.
The flash programming and the flash erasing require application of a high voltage. In order to satisfy this requisite, a transistor having a high withstand voltage and a booster circuit having a large current drive ability are necessary, and the sizes of the respective transistors constituting the booster circuit or a control circuit become larger to cause an the increase of chip areas. The attempt of reducing the chip areas by decreasing the current drive ability of the booster circuit makes the time for the programming and the erasing longer. The above problem becomes more remarkable with the recent trend of increasing the storage capacity.
JP-A-06(1994)-96592 discloses a non-volatile semiconductor memory device conducting erasing after a threshold voltage is increased. In the non-volatile semiconductor memory device in this gazette, the disadvantage that an excessively erased state is generated depending on the memory state is averted by conducting flash programming before flash erasing at the time of erasing all memory cells (all bits). In order to realize this operation, the described device has a first flash programming circuit controlling the operation of the flash programming and a second flash programming circuit functioning as a circuit for generating a high voltage and a large current at the time of the flash programming, and the flash programming is conducted block by block.
In the above gazette, a Fouler-Nordheim (F-N) tunneling method is employed for the programming in which a programming current is reduced by establishing the programming voltage to 18V even at a higher voltage side. In this non-volatile semiconductor memory device, a transistor for block selection is required in every word line to increase the chip area. A high voltage obtained by adding a threshold voltage of a block selection transistor to the programming voltage is required for the voltage to be applied to the gate of the block selection transistor. A first flash programming circuit for supplying this high voltage introduces the increase of the chip area because the same number of the circuits as that of the divided blocks are necessary.
JP-A-05(1993)-325576 discloses a non-volatile semiconductor memory device in which the erasing of a memory cell is conducted by every several blocks. In order to reduce the erasing time of the flash erasing of a plurality of the blocks, this non-volatile semiconductor memory device has a latch circuit having a function of holding erased state information. and arranged at an output stage of a row main decoder, and a row sub-decoder functioning as a block erasing section which receives an output from the latch circuit, whereas a flash erasing is performed for the plurality of blocks in accordance with information in the latch circuit. However, in this structure, the reset operations are necessary on all such occasions, and a block address latch operation and an erasing operation must be sequentially established to require a longer time for establishing the memory cell blocks to be erased by flash erasing.